Modern electronic microcircuits are typically built layer by layer on silicon chips in a series of process steps where insulating layers separate layers containing metallic, insulating and semiconducting materials that are patterned and processed by various deposition and etching techniques. Integral to the ensuing architectures are electrical connections between components and sub-circuits which are located in the substrate and in layers on top of the substrate. These connections, termed vias, are typically in the form of metallic posts or wires that penetrate through one or more layers of intervening material separating the components to be connected. Such vias are either made during the layer-building process or they are inserted through already existing layers by creating channels through the layers (by e.g. etching), followed by filling metal plugs into the channels.
Silicon chips according to prior art may involve 20–30 masking steps, and the number of separate layers containing patterned metal intra-layer leads that connect directly or indirectly to a via is typically 3–5. Each via requires a certain amount of real estate associated with it in each layer that is traversed or connected. In addition to the metal cross section of the via itself, there must be allocated a buffer zone around it which insulates the via from adjacent circuitry that shall not be in immediate contact with the via, and allowance must be made for the finite precision with which the patterning in each layer can be made as well as registration accuracy of patterning masks.
In the paper “A review of 3-D Packaging Technology” by S. F. Al-sarawi, D. Abbott and P. D. Franzon, IEEE Transactions on components, packaging, and manufacturing technology, part B, volume 21, No. 1 (February 1998), there is given a survey of the state of the art with regard to three-dimensional packaging technology aimed at large scale integration. Herein there is in several places referred to how whole stacks of integrated circuit chips can be connected mutually electrically, among other with the use of vertical vias and current paths provided on the side surfaces of circuit chip stacks, as well as the use of bonding wires for connecting respectively the mother and daughter chip where the daughter chip is provided stacked upon the mother chip, such that the exposed surface of the mother chip form a step of the stack. In this case bonding wires which are mechanically connected to contact points on the chips are used.
Wholly generally there is besides in Norwegian patent No. 308 149 and in Norwegian patent application No. 19995975 disclosed memory and data processing devices where the separate layers in the stack substantially are made with sublayers of thin film in organic material and wherein conductors at the thin films in the separate layers are conveyed to electrical edge connections on the side of the layers. In Norwegian patent application No. 19995975 the connection between the layers may additionally also be formed by vias which in principle will be fabricated as conducting structures in the same material which is included in the thin film and hence form an integral part thereof, and there is further shown a concept called “staggered vias” wherein the separate layers in a stack of this kind are provided mutually staggered and the layers in the stack connected mutually electrically or to an underlying substrate by the use of so-called staggered vias over the staggered portion. Neither in Norwegian patent 308 149 nor in Norwegian patent application No. 19995975 there are given any directions how the disclosed edge connections can be realized in a physical and practical embodiment.
The above referred prior art has generally proved inadequate for devices built on silicon substrates as mentioned above, where the number of layers and vias is low to moderate, and where ultra-high precision lithography is an integral part of the chip-making process. However, vias represent a considerable complicating feature in the overall manufacturing process, with consequences for yield and costs. Furthermore, it is expected that entirely new types of device architectures and manufacturing methods for electronic data processing and storage devices shall emerge in the next few years as serious contenders for large commercial segments. A common feature of such new architectures shall be that they incorporate thin-film electronics in dense stacks containing very large numbers of layers. In many instances, these devices will be manufactured by high-volume technologies such as reel-to-reel processing on thin polymer substrates. In this context, traditional via connection technologies shall be totally inadequate, technically as well as cost-wise.
It is a major object of the present invention to provide methods and technical solutions whereby electrical interconnects can be created between layers and/or between layers and an underlying substrate, in memory and/or processing devices that incorporate a stack containing two or more sheet- or film-like functional parts that partially or completely overlap each other. It is also an object of the present invention to provide such methods and technical solutions that can be implemented in cases where the number of such sheet- or film-like functional parts becomes large, typically exceeding 5–10.
It is a further object of the present invention to provide such methods and technical solutions that can be implemented in cases where such sheet- or film-like functional parts are manufactured and devices assembled by high-volume, low-cost technologies.
The above-mentioned objects and further features and advantages are realized according to the present invention with a device which is characterized in that one or more contact pads are provided on each step in the staggered structure in electrical connection with memory and/or processing circuits in the respective layer, and that one or more electrical edge connections are provided on and over the step in each layer in the form of electrical conducting structures on the step and over the edge between the steps in each layer and deposited on the surface of the layers, the electrical edge connections contacting one or more contact pads in the layers and providing electrical connection between each layer and also between the layers and contact pads provided on an optional substrate.
In the device according to the invention it is considered advantageous that two or more contact pads in one or more layers are mutually connected by electrical conducting structures provided on the step in the respective layer. Further there is in the device according to the invention regarded as advantageous that the electrical edge connections are provided as continuous current paths between contact pads in at least three consecutive layers in the stack or between contact pads in at least two adjacent layers in at least two adjacent layers in the stack and an optional substrate adjacent to one of these layers and/or that the electrical edge connections are provided as a patched current path between two adjacent layers in the stack or between an optional substrate and the layer adjacent to the substrate.
Preferably the stack in the device according to the invention forms at least a part of a step pyramid structure, such that the layers have different areas.
In an advantageous embodiment of the device according to the invention the separate layers in the stack are mutually displaced, such that the staggered structure comprises at least one staggered portion where the steps form an exposed portion of an upper surface in the respective layers in the stack and at least one staggered portion where the steps form an exposed portion of a lower surface in the respective layers in the stack, one or more contact pads on each step in each case being electrically connected with conducting structures respectively provided on opposite surfaces of the layers.
In another advantageous embodiment of the device according to the invention, wherein the stack is provided on a substrate, the stack forms at least a part of an inverted step pyramid-like structure, such that the area of each layer increases with the distance from the substrate, and that overlying layers are carried over the edges of underlying layers and to rest against the substrate, overlying layers being formed with one or more staggered portions, whereby the number of steps in the staggered portion of a layer corresponds to the number of layers located therebeneath, and preferably are then one or more contact pads provided in the substrate where the layers are resting against the substrate.
Finally there is in the device according to the invention regarded as advantageous that the side edge of each layer between the steps is rounded or forms an inclined surface.
The above-mentioned objects and further features and advantages are also realized according to the invention with a method which is characterized by adding each layer in the stack in separate succeeding steps, providing each succeeding layer in the stack with an area different relative to the previous adjacent layer or displaced in relation thereto, such that the stack is formed with the at least one staggered structure in one direction, steps in the staggered structure being formed by exposed portions in the provided layers, depositing structures of conducting material on the steps in each layer, such that one or more current paths and one or more contact pads are formed on each layer, and depositing continuous and/or patched electrical conducting structures which form electrical edge connections between the contact pads on two or more layers and/or between the contact pads or one or more layers and the substrate.
In the method according to the invention it is regarded as advantageous depositing depositing the layers such that the stack forms at least a part of a step pyramid structure, or depositing the layers such that the stack forms at least a part of an inverted step pyramid structure, each overlying layer being deposited over the edge of an underlying layer and to rest against the substrate, whereby overlying layers are formed with one or more staggered portions, the number of steps in each staggered portion in a layer corresponding to the number of layers located therebeneath.
In the last-mentioned case one or more contact pads are preferably provided in the substrate where the layers rest against the substrate.
Finally there is in the method according to the present invention regarded as advantageous forming the electrical edge connections in a process selected among one of the following, viz. lithography, dry etching, ink jet printing, silk printing, soft lithography, electrolysis, electrostatic deposition or in situ conversion.